In the production of a semiconductor wafer such as a silicon wafer, which is a typical example of a work to be polished, in order to obtain wafers having the flatness quality or the surface smoothness quality controlled with higher precision, a double-side polishing process is typically employed, by which top and rear surfaces of a wafer are polished simultaneously.
Especially in recent years, since semiconductor devices have been miniaturized and the diameter of semiconductor wafers has been increased, the flatness required of semiconductor wafers during light exposure has become more severe. Given this background, there is a strong need for a technique for terminating polishing in a timely manner.
FIG. 1 is a diagram showing the change in the shape of the whole surface of a wafer and the outer periphery thereof with respect to the polishing time in a typical double-side polishing process, with the relationship between the wafer thickness and the carrier plate thickness. In FIG. 1, the diagram on the left shows a cross-sectional shape in the thickness direction of the wafer, and the horizontal axis represents the distance from the wafer, where the radius of the wafer is indicated as R. An enlarged view of the surroundings of the edge of the wafer is shown on the diagram on the right. Here, in general, polishing pads that are elastic bodies are used in double-side polishing to polish the top and rear surfaces of a wafer simultaneously. Accordingly, the wafer is polished as shown in States A to E in FIG. 1.
That is, as shown in FIG. 1, in an initial stage of polishing (State A), the whole surface of the wafer has an upward convex shape, and the wafer greatly sags even in the periphery. Here, the thickness of the wafer is sufficiently larger than the thickness of a carrier plate. Next, as the polishing proceeds (State B), the whole surface of the wafer has become flatter; however, the periphery of the wafer remains sagging. Here, the thickness of the wafer is slightly larger than the thickness of the carrier plate. As the polishing proceeds further (State C), the whole wafer is almost flat and the periphery of the wafer is less sagging. Here, the thickness of the wafer is almost the same as the thickness of the carrier plate. After that, as the polishing proceeds (State D), the shape of the wafer is gradually depressed at the center, and the periphery of the wafer has a raised shape. In State D, the thickness of the carrier plate is larger than the thickness of the wafer. In State E, where the polishing has proceeded further than State D, the center of the wafer has a depressed shape, and the periphery of the wafer has an increased raise. In State E, the thickness of the carrier plate is even larger than the thickness of the wafer, as compared with State D.
In view of the above, in order to obtain a wafer having high flatness over the whole surface and the periphery, wafers have been generally polished such that the wafers have almost the same thickness as the carrier plate, and an operator has adjusted the polishing time to control the process.
However, adjustment of the polishing time performed by an operator has been significantly affected by polishing conditions such as the replacement period for the secondary materials for polishing and the differences in time of the termination of an apparatus. Accordingly, the polishing degree cannot always have been controlled accurately, so it has largely relied on the experience of the operator.
On the other hand, for example, PTL 1 proposes a double-side polishing apparatus for wafers, by which the thickness of a wafer being polished is measured in real time through monitoring holes above an upper plate (or below a lower plate), and the end time of the polishing can be determined based on the result of the measurement.